# Hermitian or not?

#### Hermitian definition

Please find if $(\overrightarrow p*\overrightarrow r)\overrightarrow L$ is hermitian or not. Please state the definition of a hermitian matrix? Which are the matrixes or $\hat r$, $\hat p$ and $\hat L$?

We write $\hat p=-i\hbar\nabla =-i\hbar (\frac{\partial }{\partial x}, \frac{\partial }{\partial y}.\frac{\partial }{\partial x})$

$\hat r= r= (x,y,z)$

and thus $\hat r*\hat p=-i\hbar (1+1+1)=-3i\hbar$

$\hat L=\hat r \times \hat p=-i\hbar \begin{pmatrix} i & i & k\\ x & y & z\\ \frac{\partial }{\partial x} & \frac{\partial }{\partial y} & \frac{\partial }{\partial z}

\end{pmatrix}$

Therefore $(\hat r,\hat p)\hat L=-3\hbar^2 \begin{pmatrix} i & i & k\\ x & y & z\\ \frac{\partial }{\partial x} & \frac{\partial }{\partial y} & \frac{\partial }{\partial z}

\end{pmatrix}$

Hence $(\hat r*\hat p)\hat L$ is hermitic if $\hat L$ is hermitic.

Matrix $\hat L$ is hermitic for two reasons (hermicity definition is $L_{ij}=L_{ji}$). First reason is that BY DEFINITION only hermitic matrixes can represent physical variables. Second reason is that the comutator $[x_i,p_j]=i\hbar\delta_{ij}$ and thus from the expression of $\hat L$ we have $L_{ij}=0$ for $i \neq j$

Therefore $\hat L$ is hermitic and so is also $(\hat r \times \hat p) \times \hat L$

#### Symmetric circuit

Please explain the circuit

The circuit is symmetric. Initially at the first moment when V11=0 V both transistors are closed. Thus their gates are at zero potential. When V11 begins to increase, both varactor (varicap) diodes open and transmit the value of the V11 to the drain of both FETs and to the gates of the FETs through capacitors C5 and C6.

(A varactor diode is a diode which opens as a normal diode when polarized direct and which capacity increases with increasing negative-reverse-voltage applied).

Now, even if the circuit is symmetric, components have tolerances. This means that one FET will open first and the other will remain closed (from V11 transmitted through the open diode, transmitted through the gate capacitor). Let say the left transistor JA opens through D1 and C6.

##### Functioning

When the transistor open, at the first moment there will be high positive induced voltage (and zero current) on its drain (from the corresponding inductor L2). Thus the cathode of D2 will have a high positive voltage which witll increase the diode reverse capacitance.

Now, the value of the current on the drain of JA (FET transistor) will begin to increase with time and the potential will begin to decrease (since JA is open). At one certain moment (depending on the value of the capacitor C5) this current and voltage potential will open through C5 the other transistor JB. The transistor JA will become blocked and the transistor JB will open.

The same repeats now on the drain of JB. Thus the circuit is a MULTIVIBRATOR. Its period depends on L2*C5=L1*C6 values. The high autoinduced voltage that is found at the first moment of FET opening on the drain inductor is transmitted through the high capacitance of the corresponding varactor diode and is found on to the R6=50 ohm load. Thus on the R6=50 ohm load there will be a voltage higher than V3 (and V11). This comes from the induced voltage on the drain inductors.